Computer Organization Class Final Project

Andrew Videmsek

Andrew Videmsek,
Junior, Electrical Engineering

Athens, OH 12 December 2016
At the end of last semester, I was assigned a final project in my Computer Organization class that was focused on designing and simulating an introductory MIPS processor. This was a very simplified version of a processor that is fairly similar to what is found in modern computers. This project took the information that we learned throughout the semester and applied it to a single problem.

Like most modern day research and development of computer hardware, we did not build the processor out of physical components, but simulated the hardware design on a computer. To do this, we used a HDL, or hardware description language, called Verilog. Verilog allows a designer to start at the lowest level, building the different types of basic gates out of transistors, and then use those basic components to continue building upward until a final design is reached.

Since this project was to encapsulate the entirety of the course, we had to start from the ground up replicating every component we learned that semester. In total we designed and tested over forty discrete components that when replicated and used to create the functions of the processor, created over 500 hardware components that were being simulated to run the processor.

When it was all said and done, and the 36-page report covering everything from the functions the processor was able to perform to the standardized input the processor must receive, it was easily one of my favorite projects of my college career. It was a project that challenged me to make sure everything I was doing was in an efficient and fault proof manner. It helped me see what I wanted to do when school was completed, and was another proof that I had chosen the correct major for myself.

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